Basic Gates
Wire
原題：Wire
GND
原題：GND
NOR
原題：NOR
Another gate
原題：Another gate
Two gates
原題：Two gates
Verilog
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = (~(in1 ^ in2))^ in3;
endmodule
More logic gates
練習各種 gate 的運算。
Verilog
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a & (~b);
endmodule
7420 chip
原題：7420 chip
稍微複雜一點的接線練習。
Verilog
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
Truth tables
原題：Truth tables
題目給了真值表，可以進一步使用卡諾圖化簡。
Verilog
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (x3 & x1) | ((~x3) & x2);
endmodule
Two-bit equality
使用三元運算子就能解決。
Verilog
module top_module ( input [1:0] A, input [1:0] B, output z );
assign z = (A == B)? 1'b1: 1'b0;
endmodule
Simple circuit A
照題目assign就行，如果從類比層面來看，not gate會比and，or，xor還小，強烈推薦多化簡成not gate。
Simple circuit B
透過觀察波形，寫出組合邏輯。
Combine circuits A and B
只是將上兩題當作當作submodule後接線。
Verilog
module top_module (input x, input y, output z);
wire wa1,wa2,wb1,wb2;
A IA1(.x(x), .y(y), .z(wa1));
A IA2(.x(x), .y(y), .z(wa2));
B IB1(.x(x), .y(y), .z(wb1));
B IB2(.x(x), .y(y), .z(wb2));
assign z = ( wa1 | wb1 ) ^ ( wa2 & wb2 );
endmodule
module A (input x, input y, output z);
assign z = x & (~y);
endmodule
module B ( input x, input y, output z );
assign z = ~(x ^ y);
endmodule
Ring or vibrate?
題目要求用gate寫出符合敘述的邏輯。
Verilog
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign motor = ring & vibrate_mode;
assign ringer = ring & (~vibrate_mode);
endmodule
Thermostat
原題：Thermostat
和前一題類似，就是依照條件接出對應的電路。
Verilog
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = (~mode) & too_hot;
assign fan = heater | aircon | fan_on;
endmodule
3-bit population count
重點是寫個全加器。
Verilog
module top_module(
input [2:0] in,
output [1:0] out );
assign out = in[2] + in[1] + in[0];
endmodule
Gates and vectors
重點是練習assign一排運算。
Verilog
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign out_both = in[2:0] & in[3:1];
assign out_any = in[2:0] | in[3:1];
assign out_different = in [3:0] ^ {in[0],in[3:1]};
endmodule
Even longer vectors
和前一題類似，只是input vector變長了。