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Arithmetic Circuits

Half adder

原題:Half adder

重點是寫一個半加器。

Verilog
module top_module( 
    input a, b,
    output cout, sum );
    assign cout = a & b;
    assign sum = a ^ b;
endmodule

Full adder

原題:Full adder

重點是寫一個全加器。

Verilog
module top_module( 
    input a, b, cin,
    output cout, sum );
    assign {cout,sum} = a + b + cin;
endmodule

3-bit binary adder

原題:3-bit binary adder

需要將3個全加器串在一起。

Verilog
module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    FA FA1(.a(a[0]),.b(b[0]),.cin(cin),.cout(cout[0]),.sum(sum[0]));
    FA FA2(.a(a[1]),.b(b[1]),.cin(cout[0]),.cout(cout[1]),.sum(sum[1]));
    FA FA3(.a(a[2]),.b(b[2]),.cin(cout[1]),.cout(cout[2]),.sum(sum[2]));
endmodule

module FA( 
    input a, b, cin,
    output cout, sum );
    assign {cout,sum} = a + b + cin;
endmodule

Adder

原題:Adder

需要將4個全加器串在一起,順便練習用generate block寫了for loop。

Verilog
module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    wire [4:1]cout;
    assign sum[4] = cout[4];
    FA FAA(.a(x[0]),.b(y[0]),.cin(1'b0),.cout(cout[1]),.sum(sum[0]));
    genvar i;
    generate
        for(i=1;i<4;i++)begin:block
            FA FAA(.a(x[i]),.b(y[i]),.cin(cout[i]),.cout(cout[i+1]),.sum(sum[i]));
        end
    endgenerate
endmodule

module FA( 
    input a, b, cin,
    output cout, sum );
    assign {cout,sum} = a + b + cin;
endmodule

Signed addition overflow

原題:Signed addition overflow

練習overflow的判別,也就是兩正數相加或兩負數相減時,分別得到負數和正數,那就是發生overflow。

Verilog
module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
);
    assign s = a + b;
    assign overflow = (a[7]&b[7]&(~s[7])) | ((~a[7])&(~b[7])&s[7]);
endmodule

100-bit binary adder

原題:100-bit binary adder

練習如何用behavioural code描述電路。

Verilog
module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    assign {cout,sum} = a + b + cin;
endmodule

4-digit BCD adder

原題:4-digit BCD adder

練習串接BCD adder。

Verilog
module top_module ( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    wire [3:0] co;
    bcd_fadd bf1(.a(a[3:0]),.b(b[3:0]),.cin(cin),.cout(co[0]),.sum(sum[3:0]));
    bcd_fadd bf2(.a(a[7:4]),.b(b[7:4]),.cin(co[0]),.cout(co[1]),.sum(sum[7:4]));
    bcd_fadd bf3(.a(a[11:8]),.b(b[11:8]),.cin(co[1]),.cout(co[2]),.sum(sum[11:8]));
    bcd_fadd bf4(.a(a[15:12]),.b(b[15:12]),.cin(co[2]),.cout(co[3]),.sum(sum[15:12]));
    assign cout = co[3];
endmodule