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Verilog⚓︎

VL1 四选一多路器⚓︎

Website: https://www.nowcoder.com/practice/cba4617e1ef64e9ea52cbb400a0725a3?tpId=301&tqId=5000604&ru=/exam/oj&qru=/ta/verilog-start/question-ranking&sourceUrl=%2Fexam%2Foj%3Fpage%3D1%26tab%3DVerilog%25E7%25AF%2587%26topicId%3D301

三元運算子就是二選一多工器,透過3個三元運算子,就能實作出一個四選一多工器。

Verilog
`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
wire [1:0]sel1, sel2;
assign mux_out = sel[1]? sel2: sel1;
assign sel2 = sel[0]? d0: d1;
assign sel1 = sel[0]? d2: d3;

//*************code***********//
endmodule


VL2 异步复位的串联T触发器⚓︎

Website: https://www.nowcoder.com/practice/9c8cb743919d405b9dac28eadecddfb5?tpId=301&tags=&title=&difficulty=0&judgeStatus=0&rp=0&sourceUrl=%2Fexam%2Foj%3Fpage%3D1%26tab%3DVerilog%25E7%25AF%2587%26topicId%3D301

這題練習將TFF接成pipeline的樣子,用always block就能寫出sequential logic。

Verilog
`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg temp;
    always@(posedge clk, negedge rst) begin
        if(!rst)begin
            temp <= 1'b0;
            q <= 1'b0;
        end
        else begin
            temp <= data ^ temp;
            q <= temp ^ q;
        end
    end

//*************code***********//
endmodule


VL3 奇偶校验⚓︎

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這題練習怎麼一次xor一串array。

Verilog
`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
//*************code***********//

assign check = !((^bus) ^ sel);
//*************code***********//
endmodule